IBM and Siemens Partner to Advance Nanostack Transistor Technology for Next-Gen Chips

Image: Illustrative image · Mark Hillary · CC BY 2.0 · Source

IBM and Siemens collaborate on design, simulation, and manufacturing research to scale IBM’s 3D nanostack transistor architecture beyond 7 angstrom node, aiming to boost performance and energy efficiency in future semiconductor chips.

On October 14, 2026, IBM announced a research collaboration with Siemens focused on advancing IBM’s nanostack architecture, a novel transistor design introduced earlier this year. Nanostack represents the semiconductor industry’s first known three-dimensional nanosheet-based transistor design, vertically stacking and staggering transistors to pack nearly 100 billion transistors within a fingernail-sized chip at the 7 angstrom node. This architecture enables individual optimization of transistor layers using different material combinations, significantly improving energy efficiency, performance, and SRAM scaling.

While IBM showcased nanostack’s viability earlier in 2026, further innovation is required to ready the technology for large-scale manufacturing and production. The partnership leverages IBM’s semiconductor device expertise with Siemens’ strengths in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software.

A key focus of the collaboration is developing advanced virtual modeling and simulation tools to optimize nanostack designs and anticipate fabrication challenges before physical chip manufacture. This co-optimization approach aims to tackle the growing physical and design complexity that emerges when scaling transistors into the angstrom era. IBM’s vice president of Silicon Technology R&D, Huiming Bu, described nanostack as a scalable platform shifting device scaling from two-dimensional to three-dimensional, providing a critical pathway to support AI and emerging technologies over the next decade.

Siemens’ Executive Vice President of EDA IC Portfolio, Ankur Gupta, emphasized the need for tightly integrated device physics, design software, and manufacturing processes in this era. He called IBM’s 3D nanostack a “pivotal leap forward” for semiconductor scaling, highlighting the importance of their joint efforts to accelerate technology cycles and production readiness.

This alliance signals a concerted push to overcome critical challenges in next-generation semiconductor scaling by combining IBM’s innovation in transistor architecture with Siemens’ capabilities in virtual design and manufacturing solution technologies. The collaboration aims to extend nanostack technology beyond the current 7 angstrom node, opening avenues for future chip generations capable of meeting escalating performance and efficiency demands in AI, telecommunications, and other advanced applications.