Tenstorrent Launches Open Source Beta of Open Chiplet Atlas Harness for Modular Chip Design

Image: Tenstorrent · Source

Tenstorrent released the open source beta of its Open Chiplet Atlas (OCA) Harness, a framework enabling interoperable chiplet security, boot, management, and connectivity, reducing engineering costs and complexity.

Tenstorrent has unveiled the open source beta release of its Open Chiplet Atlas® (OCA) Harness, a foundational framework aimed at simplifying chiplet design and integration. The OCA Harness implements the Open Chiplet Atlas interoperability architecture, which standardizes how chiplets from various vendors interoperate across software, system, protocol, transport, and physical layers.

The OCA Specification, developed to promote multi-vendor chiplet compatibility, defines rules that enable disparate chiplets to work together seamlessly. The Harness translates these specifications into a reusable hardware infrastructure addressing essential chiplet functions including security, boot processes, system management, debug and testing, and die-to-die interconnects.

By adopting the OCA Harness, chiplet teams can significantly lower non-recurring engineering (NRE) costs and reduce integration risk, allowing them to focus their resources on developing the unique application logic that differentiates their chiplets. Wei-Han Lien, Tenstorrent’s Chief CPU Architect and Senior Fellow, emphasized that the architecture liberates designers from dependence on a single vendor, while the Harness offers a reference design to ease integration challenges and accelerate custom silicon launches.

The beta release includes complete RTL source code and features three core management subsystems: the OCA Security Processor (SEP), which serves as the chiplet’s root of trust by managing secure boot, key handling, and lifecycle control; the OCA System Management Controller (SMC), responsible for clock, power, thermal, reset coordination, telemetry, and boot/configuration protocols; and Debug and Test Ports (DTP) that enable uniform cross-chiplet debug access including support for JTAG and OCA cross-trigger functionality.

Additionally, the OCA System Management Unit (SMU) integrates these subsystems, and the OCA AoU implementation supports native AXI4 traffic over UCIe die-to-die links between chiplets. To facilitate early development, the package includes a C++/SystemC virtual platform enabling firmware development prior to RTL simulation or actual silicon availability.

Several ecosystem partners contributed to this effort. BOS Semiconductors provided the original AXI over UCIe RTL, and lowRISC aided in open sourcing the Harness. Partner contributions are ongoing from VNChip Labs, which highlighted the framework’s role in reducing risk and accelerating time to silicon, and Signaloid, which noted the Harness eases integration of their compute accelerator IP into diverse systems.

Tenstorrent designed the beta version for use by early adopters, integrators, and contributors, with a full official release planned for January 2027. The OCA Harness is accessible on GitHub, accompanied by detailed documentation including guides, registers, verification status, and application notes to support developers in building interoperable chiplets under an open source Apache License 2.0.

This release marks an important step toward establishing open, vendor-neutral infrastructure for modular silicon design, promising to lower barriers and stimulate innovation within the chiplet ecosystem.