Tenstorrent and Vayavya Labs Collaborate on SystemC Virtual Platforms for RISC-V Hardware

Image: Tenstorrent · Source

Tenstorrent partners with Vayavya Labs to develop SystemC virtual platforms modeling security and system management IP, enabling earlier software testing and integration ahead of silicon availability.

Tenstorrent, a company specializing in RISC-V-based AI processors and systems, has partnered with Vayavya Labs to accelerate hardware and software development through SystemC virtual platform modeling. Since 2024, Vayavya Labs has been creating SystemC/TLM virtual platforms that simulate various subsystems of Tenstorrent’s intellectual property portfolio. These include the security enclave processor (SEP) register complexes, system management controller (SMC) logic, direct memory access (DMA) engines with secure zeroing features, boot and fuse infrastructure, and a hardware security module designed for cryptographic operations.

These virtual models allow Tenstorrent’s software development and validation teams to begin testing, development, and debugging using a virtual hardware representation long before physical silicon is produced. This early engagement aids in identifying integration issues earlier in the hardware development cycle, contributing to faster innovation and time to market.

Vayavya Labs built these models using its CSML SystemC modeling library, offering Tenstorrent an open and Accellera-compliant modeling approach alongside a commercial variant fine-tuned for their simulation environments. The use of Vayavya’s TvastaaVP platform has helped speed up development without compromising quality standards.

Recently, Vayavya Labs delivered a phased release of Tenstorrent’s Open Chiplet Harness SEP virtual platform on two independent simulation targets, enhancing it with additional system management controller and harness functions. Tenstorrent’s VP of Product Strategy, Aniket Saha, emphasized the advantage of allowing their teams to work with accurate models ahead of silicon availability, citing this as a key factor in their ongoing collaboration with Vayavya Labs.

Vayavya Labs CTO and VP Engineering, Sandeep Pendharkar, highlighted that their partnership, originally a single modeling project, has grown into a multi-year collaboration supported by the robust performance of their models under production-level demands. As Tenstorrent continues to expand its RISC-V roadmap, this virtual platform approach is expected to further enhance development velocity.

The two companies plan to discuss this collaboration further at The Open Frontier, Tenstorrent’s RISC-V ecosystem event scheduled for October 8, 2026, in Bengaluru, where Vayavya Labs’ CTO will participate in a panel discussion on RISC-V products and startups.